Verilog Code Examples With Testbench Courses
Mastering Digital VLSI, ASIC and Verilog Interview Questions
SOC, Static Timing Analysis, Synthesis, FPGA, Logic, ECOs, HDL, Digital Design, Clock Domain Crossing, Low Power Design
Rating: 4.45
Building Custom AXI Interface Peripherals for ZYNQ Devices
All about AXI Slave Lite and AXI Stream Interface
Rating: 4.4
AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog
Explanation of AMBA AXI protocol based on Xilinx Infrastructure, verilog and System verilog
Rating: 4.25
Designing a Processor with Verilog HDL and Xilinx Vivado
Step by Step Guide from Scratch
Rating: 4.15
Step by step hands-on design of UART using Verilog HDL
Understanding of UART modules and designing UART using Verilog HDL programming
Rating: 3.9
VSD - Mixed-signal RISC-V based SoC on FPGA
FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP
Rating: 3.9
Effective Verilog Learning with Intel FPGAs
The step-by-step learners guide through Intel and other FPGAs based system development.
Rating: 3.9
Digital Systems and Logic Design with verilog codes
Logic Design,Gates,Decoder,Encoder,MUX,DEMUX, Combinational Circuit design
Rating: 3.85
Systemverilog UVM interview questions and GLS simulation
Interview series on Systemverilog UVM and GLS simulation
Rating: 3.4
Learn VHDL Using Xilinx Beginner to Advanced Guide
VHDL Using Xilinx Beginner to Advanced Guide Theory and Practical also.
Rating: 2.83333
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