VSD - Clock Tree Synthesis - Part 2

VSD - Clock Tree Synthesis - Part 2

This course is a follow-up course of "VLSI Academy - Clock tree synthesis - Part 1". So its highly recommended to go through Part 1 of clock tree synthesis

Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop. 

While we plan to add some experimental videos and courses very soon, as a supplement, this one has real time examples and problems that you see on a real chip, and even solutions to those problems

The course is structured in below format:

1) Introduction

2) Clock tree optimization checklist

3) How to build clock tree for uneven spread of clock end-points

4) Power aware clock tree synthesis

5) Static timing analysis with real clocks

Sounds interesting !! Right !! So get in and have the greatest learning experience like you had never before

See you in class!!

VLSI - Building a chip is like building a city!!

Url: View Details

What you will learn

• CTS Quality Checks (Skew, Power, Latency, etc.)
• H-Tree
• Quality Check of H-Tree

Rating: 4.1

Level: All Levels

Duration: 4 hours

Instructor: Kunal Ghosh