SystemVerilog Assertions & Functional Coverage FROM SCRATCH

SystemVerilog Assertions & Functional Coverage FROM SCRATCH

SystemVerilog Assertions and Functional Coverage is a comprehensive from-scratch course on Assertions and Functional Coverage languages that cover features of SV LRM 2005/2009 and 2012. The course does not require any prior knowledge of OOP or UVM. The course is taught by a 30 year veteran in the design of CPU and SoC who has published the second edition of a book on SVA and FC in 2016 and holds 19 U.S. patents in design verification. The course has 50+ lectures and is 12+ hours in length that will take you step by step through learning of the languages.

The knowledge gained from this course will help you find and cover those critical and hard to find design bugs. SystemVerilog Assertions and Functional Coverage are very important parts of overall functional verification methodology and all verification engineers need this knowledge to be successful. The knowledge of SVA and FC will be highlights of your resume when seeking a challenging job or project. The course offers step-by-step guide to learning of SVA and FC with plenty of real life applications to help you apply SVA and FC to your project in shortest possible time. SVA and FC helps critical aspect of Functional and Sequential domain coverage which is simply not possible with code coverage.

SystemVerilog Assertions and Functional Coverage Languages/Applications FROM SCRATCH. Includes 2005/2009/2012 LRM.

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What you will learn

• Get you up and running in the shortest possible time. No knowledge of SystemVerilog OOP or UVM required
• Make you confident in spotting those critical and hard to find bugs
• The course will be a highlight of your resume

Rating: 4.48529

Level: All Levels

Duration: 12.5 hours

Instructor: Ashok B. Mehta