Verilog HDL Fundamentals for Digital Design and Verification

Verilog HDL Fundamentals for Digital Design and Verification

Are you a beginner or an enthusiastic hobbyist interested in digital circuits design using the Verilog Hardware Description Language? Did you try to learn Verilog HDL before, but found it very challenging? Are you curious if you have what it takes to become a digital chip designer or a functional verification engineer? Then you're in the right place!

Verilog Hardware Description Language easy as A,B,C

You'll learn the basics of digital circuits theory and we'll focus most of our energy on implementing practical coding examples with real digital circuits using Verilog. You will graduate this course with a strong foundation in Verilog HDL for both Digital Design and Functional Verification.

From the Digital Design perspective, you'll be able to:

• start from a digital circuit diagram / schematic and implement synthesizable Verilog code for ASIC / FPGA

• start from a functional description and implement synthesizable Verilog code for ASIC / FPGA

From the Functional Verification perspective, you'll be able to:

• understand a functional description of a digital circuit and create stimuli for it

• implement a self-checking testbench to validate the functionality of a digital circuit

You will easily differentiate between different Verilog coding styles (structural, dataflow, behavioral) and how to use them to design synthesizable digital circuits. You'll see just how easy modeling digital circuits using Verilog is!

At the end of the course you'll master Verilog industry-level coding techniques to get the best results for digital design or verification.

Learn how to use an industry-level Verilog HDL simulator

Simulations are a critical part in designing modern digital chips, thus you will install and learn how to use Modelsim - Intel FPGA Edition (free version for academic purpose).  You will be able to create projects, simulate your Verilog code, and interpret the outputs using an world-class simulator.

Course Overview

This course is tailored for beginners who are interested in digital microelectronics, digital circuit design and verification. The course contains more than 158 bite-sized lectures out of which more than half are hands-on exercises labeled Action Time. Each Action Time has downloadable resources which you can simulate immediately using Modelsim. Most of these sections also contain challenges for you, so you'll write extra code that extends beyond the initial functionality.

Your first Verilog examples will be similar to a normal programming language (like C) to learn the operators, and, step-by-step, we'll advance together to the Hardware Description Language constructs, where Verilog procedures execute in parallel.

You'll learn how to use Verilog for combinational and sequential logic and how to combine the Structural / Dataflow / Behavioral coding styles to obtain digital circuits with a specific functionality. Your circuits will get more complex as you advance, some of them being composed of a hierarchy of sub-circuits.

Verilog combinational circuits you will implement during the course :  logic gates, adders, comparator, binary encoder / decoder, priority encoder, multiplexers / de-multiplexers, seven segment display decoder, Arithmetical Logical Unit (ALU), etc...

Verilog sequential circuits you will implement during the course: flip-flops, latches, shift registers (PIPO, PISO, SIPO, SISO), Linear Feedback Shift Registers, synchronous counters, frequency dividers, Sequence Detector etc...

Next, you'll experiment with Verilog functions and tasks and how to use them in testbenches and design. 

In the final chapters you will design memories (SRAM and ROM), Finite State Machines, and more complex circuits like a FIFO and even a data encryption module.

A workflow with destination SUCCESS!

1. We start from real engineering problems and understand how a digital circuit solves that problem.

2. You are presented a real digital circuit, how it is used in the real world, then how to model and test it using Verilog.

3. You simulate it using Modelsim, and next I walk you through the results interpretation.

We do this process together every single time....  I explain the story behind the Verilog code so that, at the end of the course, you will be able to write the Verilog code behind the story.

Why learn Verilog HDL?

Chances are more than 50% that all the chips in the devices around you were designed with Verilog.

Working as a Digital Design or a Functional Verification engineer means to design today the technologies of tomorrow. This translates into having an exciting and challenging job with a great impact in the world. Since less than 2% of engineers choose this path and the semiconductor industry has never been busier, I'm pretty sure you will find yourself a good place in it.

Verilog is a good foundation for learning SystemVerilog, which is a very popular object-oriented design and verification language in the semiconductor industry.

Why did I create this course?

As an engineering student, I found it quite challenging to learn Verilog because it has a very steep learning curve and you need lots of know-how to be able to run even a simple example. Because of this, most students give up learning Verilog for a career in Digital Design or Verification and this also negatively impacts their academic results.

After 10+ years of industry experience, thousands of hours in Verilog, and academic research, I feel I've found the missing puzzle pieces that I didn't have back in the days. This course will show you the beauty and simplicity of digital circuits design using Verilog!

Ready? Set... GO!

Thank you for your interest in Verilog HDL for Digital Circuits Design and Functional Verification!

Ready to embark on your journey in mastering the basics of Verilog HDL for digital design and verification? Let's start this wonderful adventure!

Build a strong Verilog language foundation by implementing combinational / sequential digital circuits and testbenches

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What you will learn

• Master the basics of Verilog language for designing synthesizable digital circuits for ASIC / FPGA
• Differentiate between Verilog structural / dataflow / behavioral design styles and how / when to use them in Digital Design and Verification
• Implement combinational and sequential digital circuits using Verilog HDL starting from schematics or functional specifications

Rating: 4.36905

Level: Intermediate Level

Duration: 5 hours

Instructor: Ovidiu Plugariu