Synthesizable SystemVerilog for an FPGA/RTL Engineer

Synthesizable SystemVerilog for an FPGA/RTL Engineer

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. SystemVerilog plays the dominant role in the Verification Domain as well as RTL designing. The best part about both of them is once you know SystemVerilog you automatically understand the VHDL and then the capabilities of both worlds can be used to build complex systems. The course focus on the Synthesizable SystemVerilog constructs help to build RTL that can be tested on the FPGA Hardware. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain. Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite 2020 along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

Using Xilinx Vivado Design Suite 2020

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What you will learn

• SystemVerilog for building Intended RTL
• SystemVerilog Datatypes and Operators
• Modeling Styles : GATE, BEHAVIORAL, SWITCH and STRUCTURAL

Rating: 4.5

Level: All Levels

Duration: 9 hours

Instructor: Kumar Khandagle