UPF Power Aware Design & Verification

UPF Power Aware Design & Verification

Exhaustive course spanning across 6+ hours of on-demand video lectures.

Comprises of 4 major sub-sections:

Need of UPF and UPF Basics (~1 hour 1 min)

+ VLSI Design Phases
+ RTL Simulation Vs Power Aware UPF Simulation
+ UPF Basics

UPF Power Aware Design (~2 hours 51 mins)

+ Power Domains
+ Supply Nets/Ports – Power Supply Network
+ Supply Sets – Power Supply Network
+ Power Switches
+ Power State Table
+ Level Shifters
+ Isolation Cells
+ Input Vs Output Isolation Cells
+ Retention Cells
+ Flat UPF Vs Hierarchical UPF
+ UPF Evolution 1.0 Vs 2.0 Vs 2.1 Vs 3.0

UPF Power Aware Verification (~2 hours 4 mins)

+ Popular Power Saving Techniques
+ Static Verification
+ Dynamic Verification 1 – Controlling Power Supplies
+ Dynamic Verification 2 – Simstate Modelling
+ Dynamic Verification 3 – Power Coverage
+ Dynamic Verification 4 – Low Power Assertions

Miscellaneous Concepts (~11* mins)

+ Instrumentation Vs Instantiation
+ Hard Macros and Liberty Files

* New lectures might be added based upon popular user feedback and request.

Unified Power Format (IEEE1801 standard) Design and Verification Techniques

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What you will learn

• What does UPF mean and why is it required?
• UPF Low Power Design
• UPF Low Power Verification

Rating: 4.3587

Level: All Levels

Duration: 6.5 hours

Instructor: Robin Garg