Introduction to VHDL for FPGA and ASIC design

Introduction to VHDL for FPGA and ASIC design

Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process.  Explanations of the difference in sequential and concurrent VHDL.  Discussions of good synchronous design methodology.  Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.

From VHDL basics to sophisticated testbench coding

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What you will learn

• Practical FPGA and ASIC RTL design using VHDL

Rating: 4.66667

Level: Beginner Level

Duration: 9 hours

Instructor: Scott Dickson