VHDL for an FPGA Engineer with Vivado Design Suite

VHDL for an FPGA Engineer with Vivado Design Suite

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the VHDL language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain.  Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of  Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

Using Xilinx FPGA's

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What you will learn

• Fundamentals of VHDL Programming that will help to ace RTL Engineer Job Interviews.
• Understand Vivado Design Suite flow for Digital System Design.
• How to write an RTL for Synthesis

Rating: 4.32353

Level: All Levels

Duration: 19.5 hours

Instructor: Kumar Khandagle