Systemverilog UVM interview questions and GLS simulation

Systemverilog UVM interview questions and GLS simulation

System verilog UVM interview question series is an attempt to help students and professionals already having basic knowledge of the language and methodology to quickly ramp up for the interview .

The first part of the course consists of questions on

1. System verilog UVM

2. Protocol questions (SPI/I2C/AHB/APB)

3. Gate level simulation.

The second part of the course gives an introduction to gate level simulation flow .

1. Introduction - Introduction to course objectives and course requirements .

2. What is GLS - Introduction to GLS flow and challenges in running a GLS simulation .

3. Why GLS - Reasons for running a GLS simulation

4. Types of GLS simulation - introduction to zero delay , unit delay , SDF simulation .

5. Bugs found in GLS simulation - common bug types found only in GLS simulation.
   

Interview series on Systemverilog UVM and GLS simulation

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What you will learn

• System verilog UVM interview questions
• Common protocol questions (SPI/I2C/AHB/APB)
• Gate level simulation

Rating: 3.4

Level: Intermediate Level

Duration: 1 hour

Instructor: Kiran Bhaskar