Video Processing with FPGA

Video Processing with FPGA

This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IP from the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGA Device.

We have "Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm" on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement.

After Completing this course you will be able to:

1. Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLS

2. Integrating the HLS IP with Video Processing Pipeline with TPG and VDMA and Implementing on the FPGA Device.

3. Implementing the XfOpenCV [SDSoC] Library on HLS for Computer Vision

4. Migrating the OpenCV algorithm into XfOpenCV

Implementing different Computer Vision Algorithm on Xilinx Zynq FPGA with VIVADO High Level Synthesis & SDK

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What you will learn

• Implement different Computer Vision algorithm for Video Processing
• Creating IP from the VIVADO High Level Synthesis
• IP integration and configuration with Xilinx VIVADO

Rating: 3.25

Level: All Levels

Duration: 4.5 hours

Instructor: Digitronix Nepal