VSD - SoC Design of the PicoRV32 RISCV micro-processor

VSD - SoC Design of the PicoRV32 RISCV micro-processor

This webinar was conducted on 2nd June 2018

After successful webinar on Making of Raven Chip, this time we take the chip forward and implement using end-to-end opensource EDA tools, and all on efabless cloud. What does this mean to us? It means, you can start innovating on a design, build RTL and do synth/PD/LVS/DRC all using opensource EDA framework and not pay a single penny for license.

The big question How is this possible? Thereby, I welcome you all to my next (follow-up) webinar with Tim Edwards and Mohamed Kassem

About instructors -

Tim Edwards

Tim Edwards has been doing analog VLSI design and collecting and developing open-source EDA tools for over 25 years.  He has worked for the Johns Hopkins Applied Physics Lab, startups MultiGiG (bought by Analog Devices) and most recently, eFabless. 

Mohamed Kassem

Mohamed Kassem is the cofounder and CTO of eFabless corporation. Prior to launching eFabless in 2014, Mohamed held several technical and global leadership positions within TI's Wireless Business Unit. He joined TI in 2000 at the beginning of the digital telephony revolution fueled by the unprecedented integration of major phone functions on a single SoC. He led the first development of 45nm, 28nm analog & mixed-signal IP functions for wireless applications processors. Mohamed holds a masters degree in electrical engineering from the University of Waterloo, Ontario, Canada.

Freedom to build micro-processors

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What you will learn

• Run a full physical design flow from RTL design to GDSII, making it ready for tape-out.
• For freshers, this course will make them industry ready and might increase their chances of getting placed or work for tier-1 company
• For experienced VLSI Physical design professionals, this will give a bigger picture of SoC physical design, which is appplication specific

Rating: 3.95

Level: Intermediate Level

Duration: 4 hours

Instructor: Kunal Ghosh