FPGA Design with VIVADO HLS & Vitis HLS-High Level Synthesis

FPGA Design with VIVADO HLS & Vitis HLS-High Level Synthesis

At the ending of this course, we also have included how to "install Vitis HLS, setup OpenCV in Vitis HLS and performing the Vitis Vision 2020.2 based examples".

Learn from Basic HLS Design & C-Simulation to Design Computer Vision Application [Real Time Sobel Edge Detection]

High Level Synthesis is new approach on FPGA Design with C/C++ Language.This Course covers : Creating new project on HLS, Running C Simulation on HLS, Synthesizing the HLS Project's which converts C/C++ Source in to Verilog/VHDL and System C, Running C/RTL Co-simulation, Exporting HLS Design in to IP core Format  to VIVADO IP Integrator. We also have include session on "Sobel Edge IP design in HLS, exporting it to VIVADO tool and then implementing/testing it on Zybo FPGA".

After Completing this course you will be able to Design, Simulate,Synthesize and Implement/Export HLS projects. HLS includes large number of C/C++ Libraries for Computer Vision (OpenCV), Video/Image Processing and Mathematical Computations which is very much complex while implementing on HDL/RTL.

In this Lab you are going to do lab on Design, Simulation , Synthesis and Implementation (Export Design) of Counter, Matrix Multiplier, Frequency Modulator, Numerically Controlled Oscillator (NCO Design) in C++. You will also integrate the exported HLS project with Zynq Processing System at VIVADO IP Integrator and Synthesize, Implement the Project on VIVADO IPI.

Design, Simulate, Synthesize & Export IP with VIVADO HLS & Vitis HLS : An FPGA Design Approach with C/C++

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What you will learn

• Vitis HLS Installation, OpenCV Setup and LAB session
• Image Processing with VIVADO HLS & FPGA: Utilizing Computer Vision & Image/Video Processing Libraries on HLS
• Sobel Edge Detection IP design in HLS, integrate IP in VIVADO tool and implement it on Zynq FPGA

Rating: 3.3

Level: All Levels

Duration: 4 hours

Instructor: Digitronix Nepal